View ADF4113HV_6365831.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

high voltage charge pump, pll synthesizer ADF4113HV rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features high voltage charge pump (15 v) 2.7 v to 5.5 v power supply 200 mhz to 4.0 ghz frequency range pin compatible with adf4110, adf4111, adf4112, adf4113 adf4106, and adf4002 synthesizers two selectable charge pump currents digital lock detect power-down mode loop filter design possible with adisimpll? applications applications using high voltage vcos if/rf local oscillator (lo) generation in base stations point-to-point radio lo generation clock for analog-to-digital and digital-to-analog converters wireless lans, pmr communications test equipment general description the ADF4113HV is an integer-n frequency synthesizer with a high voltage charge pump (15 v). the synthesizer is designed for use with voltage controlled oscillators (vcos) that have high tuning voltages (up to 15 v). active loop filters are often used to achieve high tuning voltages, but the ADF4113HV charge pump can drive a high voltage vco directly with a passive-loop filter. the ADF4113HV can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. it consists of a low noise digital phase frequency detector (pfd), a precision high voltage charge pump, a programmable reference divider, programmable a and b counters, and a dual-modulus prescaler (p/p + 1). a simple 3-wire interface controls all of the on-chip registers. the devices operate with a power supply ranging from 2.7 v to 5.5 v and can be powered down when not in use. functional block diagram clk data le muxout ADF4113HV cp ce agnd dgnd cpgnd 22 14 reference m3 m2 m1 6 high z n=bp+a charge pump current setting mux r set v p phase frequency detector lock detect av dd sd out 24-bit input register d v dd a v dd 19 13 sd out ref in 14-bit r counter rf in a rf in b rcounter latch function latch a, b counter latch from function latch 13-bit b counter 6-bit acounter prescaler p/p + 1 06223-001 load load figure 1.
ADF4113HV rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 4 absolute maximum ratings ............................................................ 5 transistor count ........................................................................... 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 7 circuit description ........................................................................... 9 reference input section ............................................................... 9 rf input stage ............................................................................... 9 prescaler (p/p + 1) ........................................................................9 a and b counters ..........................................................................9 r counter .......................................................................................9 phase frequency detector (pfd) and charge pump ............ 10 muxout and lock detect ........................................................... 10 input shift register .................................................................... 10 function latch ............................................................................ 13 applications ..................................................................................... 15 using a digitial-to-analog converter to drive the r set pin .................................................................................. 15 interfacing ................................................................................... 15 pcb design guidelines for chip scale package .................... 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revision history 1/07revision 0: initial version
ADF4113HV rev. 0 | page 3 of 20 specifications av dd = dv dd = 3 v 10%, 5 v 10%; 13.5 v < v p 16.5 v; agnd = dgnd = cpgnd = 0 v; r set = 4.7 k; dbm referred to 50 ; t a = t min to t max , unless otherwise noted. operating temperature range for b version: ?40c to +85c. table 1. parameter b version b chips 1 unit test conditions/comments rf characteristics (3 v) rf input sensitivity ?15/0 ?15/0 dbm min/max rf input frequency 0.2/3.7 0.2/3.7 ghz min/max for lower frequencies, ensure sr > 130 v/s prescaler output frequency 2 165 165 mhz max rf characteristics (5 v) rf input sensitivity ?10/0 ?10/0 dbm min/max rf input frequency 0.2/3.7 0.2/3.7 ghz min/max for lower frequencies, ensure sr > 130 v/s 0.2/4.0 0.2/4.0 ghz min/max input level = ?5 dbm prescaler output frequency 200 200 mhz max ref in characteristics ref in input frequency 5/150 5/150 mhz min/max for f < 5 mhz, ensure sr > 100 v/s reference input sensitivity 0.4/av dd 0.4/av dd v p-p min/max av dd = 3.3 v, biased at av dd /2 3 1.0/av dd 1.0/av dd v p-p min/max for f 10 mhz, av dd = 5 v, biased at av dd /2 3 , 4 ref in input capacitance 10 10 pf max ref in input current 100 100 a max phase detector frequency 5 5 mhz max charge pump i cp sink/source r set = 4.7 k high value 640 640 a typ low value 80 80 a typ absolute accuracy 2.5 2.5 % typ r set range 3.9/10 3.9/10 k typ i cp three-state leakage current 5 5 na max sink and source current matching 3 3 % typ 1 v v cp v p C 1 v i cp vs. v cp 1.5 1.5 % typ 1 v v cp v p C 1 v i cp vs. temperature 2 2 % typ v cp = v p /2 logic inputs v inh , input high voltage 0.8 dv dd 0.8 dv dd v min v inl , input low voltage 0.2 dv dd 0.2 dv dd v max i inh /i inl , input current 1 1 a max c in , input capacitance 10 10 pf max logic outputs v oh , output high voltage dv dd ? 0.4 dv dd ? 0.4 v min i oh = 500 a v ol , output low voltage 0.4 0.4 v max i ol = 500 a power supplies av dd 2.7/5.5 2.7/5.5 v min/v max dv dd av dd av dd v p 13.5/16.5 13.5/16.5 v min/v max i dd 5 (ai dd dd + di ) 16 11 ma max 11 ma typical i p 0.25 0.25 ma max t a = 25c low power sleep mode 1 1 a typ noise characteristics normalized phase noise floor 6 ?212 ?212 dbc/hz typ 1 the b chip specifications are given as typical values. 2 this is the maximum operating frequency of the cmos counters. the prescaler value should be chosen to ensure that the rf input is divided down to a frequency that is less than this value. 3 ac coupling ensures av dd /2 bias. 4 guaranteed by characterization. 5 t a = 25 o c; av dd = dv dd = 5.5 v; p = 16; rf in = 900 mhz. 6 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco, pn tot , and subtracting 20logn (where n is the n divider value) and 10logf pfd : pn synth = pn tot ? 10logf pfd ? 20logn.
ADF4113HV rev. 0 | page 4 of 20 timing characteristics guaranteed by design but not production tested. av dd = dv dd = 3 v 10%, 5 v 10%; 13.5 v v p 16.5 v; agnd = dgnd = cpgnd = 0 v; r set = 4.7 k; t a = t min to t max , unless otherwise noted. table 2. parameter limit at t min to t max (b version) unit test conditions/comments t 1 20 ns min le setup time t 2 10 ns min data to clk setup time t 3 10 ns min data to clk hold time t 4 25 ns min clk high duration t 5 25 ns min clk low duration t 6 10 ns min clk to le setup time t 7 20 ns min le pulse width timing diagram clk data le le db23 (msb) db22 db2 db1 (control bit c2) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 06223-002 figure 2. timing diagram
ADF4113HV rev. 0 | page 5 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to gnd 1 ?0.3 v to +7 v av dd to dv dd ?0.3 v to +0.3 v v p to gnd ?0.3 v to +18 v digital i/o voltage to gnd ?0.3 v to v dd + 0.3 v analog i/o voltage to gnd ?0.3 v to v p + 0.3 v ref in , rf in a, rf in b to gnd ?0.3 v to v dd + 0.3 v rf in a to rf in b 320 mv operating temperature range industrial (b version) ?40c to +85c storage temperature range ?65c to +150c maximum junction temperature 150c lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c 1 gnd = agnd = dgnd = 0 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of <1 kv, and it is esd sensitive. proper precautions should be taken for handling and assembly. transistor count the transistor count is 12,150 (cmos) and 348 (bipolar). thermal resistance table 4. thermal resistance package type ja unit tssop 150.4 c/w lfcsp (paddle soldered) 122 c/w lfcsp (paddle not soldered) 216 c/w esd caution
ADF4113HV rev. 0 | page 6 of 20 pin configurations and function descriptions 1 2 3 4 5 6 7 8 cp c pgnd agnd av dd r fin a r fin b r set ref in 16 15 14 13 12 11 10 9 dv dd muxout le ce dgnd clk data v p ADF4113HV top view (not to scale) 0 6223-003 figure 3. tssop pin configuration pin 1 indicator 1 cpgnd 2 agnd 3 agnd 4 rf in b 5 rf in a 13 data 14 le 15 muxout 12 clk 11 ce 6 a v d d 7 a v d d 8 r e f i n 1 0 d g n d 9 d g n d 1 8 v p 1 9 r s e t 2 0 c p 1 7 d v d d 1 6 d v d d ADF4113HV top view (not to scale) 06223-004 figure 4. lfcsp pin configuration table 5. pin function descriptions tssop pin no. lfcsp pin no. mnemonic description 1 19 r set connecting a resistor between this pin and cpgnd sets the maximum charge pump output current. the nominal voltage potential at the r set pin is 0.56 v for the ADF4113HV. the relationship between i cp and r set is i cpmax = 3/r set . therefore, with r set = 4.7 k, i cpmax = 640 a. 2 20 cp charge pump output. when enabled, this pin provides i cp to the external loop filter; in turn, this drives the external vco. 3 1 cpgnd charge pump ground. cpgnd is the ground return path for the charge pump. 4 2, 3 agnd analog ground. this is the ground return path of the prescaler. 5 4 rf in b complementary input to the rf prescaler. this point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pf. 6 5 rf in a input to the rf prescaler. this small-si gnal input is ac-coupled from the vco. 7 6, 7 av dd analog power supply. the power supply can range from 2.7 v to 5.5 v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. av dd must be the same value as dv dd . 8 8 ref in reference input. this pin is a cmos input with a nominal threshold of v dd /2, and an equivalent input resistance of 100 k. this input can be driven from a ttl or cmos crystal oscillator, or can be ac-coupled. 9 9, 10 dgnd digital ground. 10 11 ce chip enable. a logic low on this pin powers down the device and puts the charge pump output into three-state mode. taking the pin high powers up the device depending on the status of the power-down bit pd1. 11 12 clk serial clock input. this serial clock is used to cloc k in the serial data to the registers. the data is latched into the 24-bit shift register on the clk ri sing edge. this input is a high impedance cmos input. 12 13 data serial data input. the serial data is loaded msb first with the two lsbs being the control bits. this input is a high impedance cmos input. 13 14 le load enable, cmos input. when le goes high, the da ta stored in the shift registers is loaded into one of the four latches; the latch is selected using the control bits. 14 15 muxout multiplexer output. this multiplexer output allows either the lock detect, the scaled rf, or the scaled reference frequency to be externally accessed. 15 16, 17 dv dd digital power supply. this can range from 2.7 v to 5. 5 v. decoupling capacitors to the digital ground plane (1f, 1nf) should be placed as close as possible to this pin. for best performance, the 1 f capacitor should be placed within 2 mm of the pin. the placing of the 1nf capacitor is less critical but should still be within 5 mm of the pin. dv dd must have the same value as av dd . 16 18 v p charge pump power supply. v p can range from 13.5 v to 16.5 v and should be decoupled appropriately.
ADF4113HV rev. 0 | page 7 of 20 typical performance characteristics loop bandwidth = 25 khz, reference = 10 mhz reference from ag ilent e4440a psa, vco = sirenza vco190-1500t(y), evaluation board = eval-ADF4113HVebz1. freq ?unit param ?type data ?format keyword impedance ?ohms ghz s ma r 50 freq mags11 angs11 1.05 0.9512 ?40.134 1.10 0.93458 ?43.747 1.15 0.94782 ?44.393 1.20 0.96875 ?46.937 1.25 0.92216 ?49.6 1.30 0.93755 ?51.884 1.35 0.96178 ?51.21 1.40 0.94354 ?53.55 1.45 0.95189 ?56.786 1.50 0.97647 ?58.781 1.55 0.98619 ?60.545 1.60 0.95459 ?61.43 1.65 0.97945 ?61.241 1.70 0.98864 ?64.051 1.75 0.97399 ?66.19 1.80 0.97216 ?63.775 freq mags11 angs11 0.05 0.89207 ?2.0571 0.10 0.8886 ?4.4427 0.15 0.89022 ?6.3212 0.20 0.96323 ?2.1393 0.25 0.90566 ?12.13 0.30 0.90307 ?13.52 0.35 0.89318 ?15.746 0.40 0.89806 ?18.056 0.45 0.89565 ?19.693 0.50 0.88538 ?22.246 0.55 0.89699 ?24.336 0.60 0.89927 ?25.948 0.65 0.87797 ?28.457 0.70 0.90765 ?29.735 0.75 0.88526 ?31.879 0.80 0.81267 ?32.681 0.85 0.90357 ?31.522 0.90 0.92954 ?34.222 0.95 0.92087 ?36.961 1.00 0.93788 ?39.343 06223-005 figure 5. s-parameter data for the ADF4113HV rf input (up to 1.8 ghz) 0 ?45 06 k 06223-027 rf input frequency (mhz) rf input power (dbm) ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 1k 2k 3k 4k 5k +25c +85c ?40c figure 6. input sensitivity 100 1m 06223-042 frequency offset (hz) 1k 10k 100k 1khz ?91.08dbc/hz ?80 ?90 ? 70 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 phase noise (dbc/hz) carrier power: ?5.09dbm figure 7. integrated phase noise (rf = 1000 mhz, pfd = 1 mhz, v tune = 1.8 v, rms noise = 0.93) 5 ?95 ?1.25m ?1.00m ?0.75m ?0.50m ?0.25m 1.00g 0.25m 0.50m 0.75m 1.00m 1.25m 06223-043 frequency (hz) power (db) ?5 ?15 ?25 ?35 ?45 ?55 ?65 ?75 ?85 1mhz ?92.428dbc figure 8. reference spurs (rf = 1000 mhz, pfd = 1 mhz) ? 100 1m 06223-040 frequency offset (hz) 1k 10k 100k 1khz ?86.33dbc/hz ?80 ?90 70 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 phase noise (dbc/hz) carrier power: ?0.88dbm figure 9. integrated phase noise (rf = 1800 mhz, pfd= 1 mhz, v tune = 13.1 v, rms noise = 1.16) 0 ?100 ?1.25m ?1.00m ?0.75m ?0.50m ?0.25m 1.00g 0.25m 0.50m 0.75m 1.00m 1.25m 06223-041 frequency (hz) power (db) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 1mhz ?87.264dbc figure 10. reference spurs (rf = 1800 mhz, pfd = 1 mhz)
ADF4113HV rev. 0 | page 8 of 20 06223-044 tuning voltage (v) 0 ?120 01 6 800 ?800 01 5 06223-026 v cp (v) charge pump current (a) first reference spur level (dbc) v dd = 3v v p = 15v 600 400 200 0 ?200 ?400 ?600 ?20 ?40 ?60 ?80 ?100 2468101214 1234567891011121314 figure 11. pfd spurs (1 mhz) vs. v tune ? 50 ?90 ?40 100 06223-045 temperature (c) phase noise (dbc/hz) ?60 ?70 ?80 ?20 0 20 40 60 80 v dd = 3v v p = 15v figure 12. phase noise vs. temperature (rf = 1500 mhz, pfd = 1 mhz) figure 13. charge pump output characteristics
ADF4113HV rev. 0 | page 9 of 20 circuit description reference input section the reference input stage is shown in figure 14 . sw1 and sw2 are normally closed switches (nc in figure 14 ). sw3 is normally open (no in figure 14 ). when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. buffer to r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down control 06223-014 figure 14. reference input stage rf input stage the rf input stage is shown in figure 15 . it is followed by a two-stage limiting amplifier to generate the current-mode logic (cml) clock levels needed for the prescaler. av dd agnd 500 ? 500 ? 1.6v bias generator rf in a rf in b 06223-015 figure 15. rf input stage prescaler (p/p + 1) together with the a and b counters, the dual-modulus prescaler (p/p + 1) enables the large division ratio, n, to be realized by n = bp + a the dual-modulus prescaler, operating at cml levels, takes the clock from the rf input stage and divides it down to a manageable frequency for the cmos a and cmos b counters. the pre- scaler is programmable; it can be set in software to 8/9, 16/17, 32/33, or 64/65. it is based on a synchronous 4/5 core. a and b counters the a and b cmos counters combine with the dual-modulus prescaler to allow a wide ranging division ratio in the pll feedback counter. the counters are specified to work when the prescaler output is 200 mhz or less (for av dd = 5 v). thus, with an rf input frequency of 2.5 ghz, a prescaler value of 16/17 is valid but a value of 8/9 is not. pulse swallow function the a and b counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by r. the equation for the vco frequency is f vco = [( p b ) + a ] f refin / r where: f vco = output frequency of external voltage controlled oscillator (vco). p = preset modulus of dual-modulus prescaler. b = preset divide ratio of binary 13-bit counter (3 to 8191). a = preset divide ratio of binary 6-bit swallow counter (0 to 63). f refin = output frequency of the external reference frequency oscillator. r = preset divide ratio of binary 14-bit programmable reference counter (1 to 16,383). 13-bit b counter 6-bit a counter prescaler p/p + 1 from rf input stage modulus control n=bp+a load load to pfd 0 6223-016 figure 16. a and b counters r counter the 14-bit r counter allows the input reference frequency to be divided down to produce the reference clock to the phase fre- quency detector (pfd). division ratios from 1 to 16,383 are allowed.
ADF4113HV rev. 0 | page 10 of 20 phase frequency detector (pfd) and charge pump the pfd takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 17 is a simplified schematic. the pfd includes a programmable delay element that controls the width of the antibacklash pulse. this pulse ensures that there is no dead zone in the pfd transfer function and mini- mizes phase noise and reference spurs. two bits in the reference counter latch, abp2 and abp1, control the width of the pulse. see figure 20 . the only recommended setting for the antiback- lash pulse width is 7.2 ns. programmable delay u3 clr2 q2 d2 u2 clr1 q1 d1 charge pump down up high high u1 abp1 abp2 r divider n divider cp output r divider n divider cp cpgnd v p 0 6223-017 figure 17. pfd simplified sche matic and timing (in lock) muxout and lock detect the output multiplexer on the ADF4113HV allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m2, and m1 in the function latch. figure 22 shows the full truth table (function latch map). figure 18 shows the muxout section in block diagram form. control mux d v dd muxout dgnd a n a log lock detect digital lock detect r counter output n counter output sdout 06223-018 figure 18. muxout circuit lock detect muxout can be programmed for two types of lock detect: digital lock detect and analog lock detect. digital lock detect is active high. when ldp in the ab counter latch is set to 0, digital lock detect is set high when the phase error on five consecutive phase detector (pd) cycles is less than 10 ns. with ldp set to 1, five consecutive cycles of less than 3 ns are required to set the lock detect. it stays high until a phase error greater than 25 ns is detected on any subsequent pd cycle. operate the n-channel, open-drain, analog lock detect with a 10 k nominal external pull-up resistor. when lock has been detected, this output is high with narrow low-going pulses. input shift register the ADF4113HV digital section includes a 24-bit input shift register, a 14-bit r counter, and a 19-bit n counter comprising a 6-bit a counter and a 13-bit b counter. data is clocked into the 24-bit shift register on each rising edge of clk, msb first. data is transferred from the shift register to one of three latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2, c1) in the shift register. these are the two lsbs, db1 and db0, as shown in figure 2 . the truth table for these bits is shown in table 6 . figure 19 shows a summary of how the latches are programmed. table 6. c2, c1 truth table control bits c2 c1 data latch 0 0 r counter 0 1 n counter (a and b) 1 0 function latch (including prescaler)
ADF4113HV rev. 0 | page 11 of 20 latch summary db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 000000abp2abp1r14r13r12r11r10r9r8r7r6r5r4r3r2r1c2(0)c1(0) reserved 14-bit reference counter control bits reference counter latch db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 l1 0 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 a6 a5 a4 a3 a2 a1 c2(0) c1(1) control bits re- served ld prec re- served 13-bit b counter 6-bit a counter n counter latch db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 p2p10000cp3cp2cp1000000f4f3m3m2m1f2f1c2(1)c1(0) control bits cp three- state pd polarity pre- scaler value reserved current setting reserved muxout control power down counter reset function latch 06223-019 anti- backlash pulse width figure 19. latch summary tables reference counter latch map db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db1 3 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 000000abp2abp1r14r13r12r11r10r9r8r7r6r5r4r3r2r1c2(0)c1(0 ) reserved anti- backlash pulse width 14-bit reference counter control bits these bits must be set as indicated for normal operation r14 r13 r12 .......... r3 r2 r1 divide ratio 0 0 0 .......... 0 0 1 1 0 0 0 .......... 0 1 0 2 0 0 0 .......... 0 1 1 3 0 0 0 .......... 1 0 0 4 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 16380 1 1 1 .......... 1 0 1 16381 1 1 1 .......... 1 1 0 16382 1 1 1 .......... 1 1 1 16383 06223-020 abp2 abp1 anti-backlash pulse width 1 0 7.2ns (only allowed setting) figure 20. reference counter latch bit map
ADF4113HV rev. 0 | page 12 of 20 ab counter latch map db23 db22 db21 db20 db19 db18 db1 7 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 a6 a5 a4 a3 a2 a1 c2(0) c1(1) control bits re- served ld prec re- served 13-bit b counter 6-bit a counter l2 lock detect precision 0 10ns 13ns b13 b12 b11 b3 b2 b1 b counter divide ratio 0 0 0 .......... 0 0 0 not allowed 0 0 0 .......... 0 0 1 not allowed 0 0 0 .......... 0 1 0 not allowed 0 0 0 .......... 1 1 1 3 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 8188 1 1 1 .......... 1 0 1 8189 1 1 1 .......... 1 1 0 8190 1 1 1 .......... 1 1 1 8191 a6 a5 a2 a1 a counter divide ratio 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 0 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 1 61 1 1 .......... 1 0 62 1 1 .......... 1 1 63 06223-021 figure 21. b counter latch map
ADF4113HV rev. 0 | page 13 of 20 function latch map db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 p2p10000cp3cp2cp1000000f4f3m3m2m1f2f1c2(1)c1(0) control bits cp three- state pd polarity pre- scaler value reserved current setting reserved muxout control power down counter reset p2 p1 prescaler value 008/9 0116/17 1032/33 1164/65 i cp (a) cpi3 cpi2 cpi1 4.7k ? 00080 111640 f4 charge pump output 0normal 1 three-state f3 phase detector polarity 0 positive 1negative m3 m2 m1 output 0 0 0 three-state output 0 0 1 digital lock detect (active high) 0 1 0 n divider output 011dv dd 1 0 0 r divider output 1 0 1 analog lock detect 1 1 0 serial data output 1 1 1 dgnd pd1 operation 0normal 1power down f1 counter operation 0normal 1 r, a, b counters held in reset 06223-022 figure 22. function latch map function latch the on-chip function latch is programmed with c2 and c1 set to 1,0, respectively. figure 22 shows the input data format for programming the function latch. counter reset db2 (f1) is the counter reset bit. when db2 is 1, the r counter and the ab counters are reset. for normal operation, this bit should be 0. upon powering up, the f1 bit must be disabled, and the n counter resumes counting in close alignment with the r counter. (the maximum error is one prescaler cycle.) power-down db3 (f2) in the function latch provides a software power-down for the ADF4113HV. the device powers down immediately after latching a 1 into bit f2. when the ce pin is low, the device immediately powers down regardless of the state of the power-down bit (f2). when a power-down is activated (either through software or a ce pin activated power-down), the following events occur: ? all active dc current paths are removed. ? the r, n, and timeout counters are forced to their load state conditions. ? the charge pump is forced into three-state mode. ? the digital clock detect circuitry is reset. ? the rf in a and rf in b inputs are debiased. ? the reference input buffer circuitry is disabled. ? the input register remains active and capable of loading and latching data. muxout control the on-chip multiplexer is controlled by m3, m2, and m1 on the ADF4113HV. figure 22 shows the truth table. charge pump currents cpi3, cpi2, and cpi1 program the current setting for the charge pump. the truth table is given in figure 22 . prescaler value p2 and p1 in the function latch set the prescaler values. the prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 200 mhz. thus, with an rf frequency of 2 ghz, a prescaler value of 16/17 is valid, but a value of 8/9 is not. pd polarity this bit sets the phase detector polarity bit. see figure 22 . cp three-state this bit controls the cp output pin. with the bit set high, the cp output is put into three-state. with the bit set low, the cp output is enabled.
ADF4113HV rev. 0 | page 14 of 20 device programming after initial power-up after initial power-up of the device, there are two ways to program the device. ce pin method 1. apply v dd . 2. bring ce low to put the device into power-down. this is an asynchronous power-down in that it happens immediately. 3. program the function latch (10). program the r counter latch (00). program the ab counter latch (01). 4. bring ce high to take the device out of power-down. the r and ab counters resume counting in close alignment. after ce goes high, a duration of 1 s is sometimes required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. ce can be used to power the device up and down to check for channel activity. the input register does not need to be repro- grammed each time the device is disabled and enabled as long as it has been programmed at least once after v dd was initially applied. counter reset method 1. apply v dd . 2. conduct a function latch load (10 in 2 lsbs). as part of this, load 1 to the f1 bit. this enables the counter reset. 3. conduct an r counter load (00 in 2 lsbs). 4. conduct an ab counter load (01 in 2 lsbs). 5. conduct a function latch load (10 in 2 lsbs). as part of this, load 0 to the f1 bit. this disables the counter reset. this sequence provides the same close alignment as the initiali- zation method. it offers direct control over the internal reset. note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down.
ADF4113HV rev. 0 | page 15 of 20 applications ADF4113HV 2.7k ? vco gnd 18 ? 100pf 100pf 18 ? 18 ? rf out fref in 51? 100pf 100pf rf in a rf in b r set ref in cp ce clk data le spi-compatible serial bus muxout lock detect input output 2 14 6 5 1 8 loop filter notes 1. power supply connections and decoupling capacitors are omitted for clarity. ad5320 12-bit v-out dac 06223-023 figure 23. driving the r set pin with a digital-to-analog converter using a digitial-to-analog converter to drive the r set pin a digital-to-analog converter (dac) can be used to drive the r set pin of the ADF4113HV, thus increasing the level of control over the charge pump current (i cp ). this can be advantageous in wideband applications where the sensitivity of the vco varies over the tuning range. to compensate for this, i cp can be varied to maintain good phase margin and ensure loop stability. see figure 23 for this configuration. interfacing the ADF4113HV has a simple spi?-compatible serial interface for writing to the device. clk, data, and le control the data transfer. when latch enable (le) goes high, the 24 bits that have been clocked into the input register on each rising edge of clk are transferred to the appropriate latch. see figure 2 for the timing diagram and table 6 for the latch truth table. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible for the device is 833 khz, or one update every 1.2 s. this rate is more than adequate for systems that have typical lock times in the hundreds of microseconds. aduc812 interface figure 24 shows the interface between the ADF4113HV and the aduc812 microconverter?. because the aduc812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the ADF4113HV needs a 24-bit word. this is accomplished by writing three 8-bit bytes from the microconverter to the device. when the third byte has been written, the le input should be brought high to complete the transfer. i/o port lines on the aduc812 are also used to control power- down (ce input), and to detect lock (muxout configured as lock detect and polled by the port input). when the aduc812 is operating in the spi master mode, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed is 166 khz. sclock mosi i/o ports aduc812 clk data le ce muxout (lock detect) ADF4113HV 06223-024 figure 24. aduc812 to ADF4113HV interface
ADF4113HV rev. 0 | page 16 of 20 adsp-21xx interface figure 25 shows the interface between the ADF4113HV and the adsp-21xx digital signal processor. the ADF4113HV needs a 24-bit serial word for each latch write. the easiest way to accomplish this using the adsp-21xx family is to use the auto buffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. sclk dt i/o flags adsp-21xx clk data le ce muxout (lock detect) ADF4113HV tfs 06223-025 figure 25. adsp-21xx to ADF4113HV interface set up the word length for eight bits and use three memory locations for each 24-bit word. to program each 24-bit latch, store the three 8-bit bytes, enable the auto buffered mode, and then write to the transmit register of the dsp. this last opera- tion initiates the autobuffer transfer. pcb design guidelines for chip scale package the lands on the chip scale package (cp-20-1) are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length, and 0.05 mm wider than the package land width. the land should be centered on the pad to ensure that the solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. on the printed circuit board, provide a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. this ensures that shorting is avoided. thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. the user should connect the printed circuit board thermal pad to agnd.
ADF4113HV rev. 0 | page 17 of 20 outline dimensions 1 20 5 6 11 16 15 10 2.25 2.10 sq 1.95 0.75 0.55 0.35 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicato r top view 3.75 bcs sq 4.00 bsc sq coplanarity 0.08 0.60 max 0.60 max 0.25 min compliant to jedec standards mo-220-vggd-1 pin 1 indicator figure 26. 20-lead lead frame chip scale package [lfcsp_vq] 4 mm x 4 mm body, very thin quad (cp-20-1) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 27. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters ordering guide model temperature range package description package option ADF4113HVbruz 1 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 ADF4113HVbruz-rl 1 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 ADF4113HVbruz-rl7 1 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 ADF4113HVbcpz 1 ?40c to +85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 ADF4113HVbcpz-rl 1 ?40c to +85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 ADF4113HVbcpz-rl7 1 ?40c to +85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 eval-ADF4113HVeb1z 1 evaluation board 1 z = pb-free part.
ADF4113HV rev. 0 | page 18 of 20 notes
ADF4113HV rev. 0 | page 19 of 20 notes
ADF4113HV rev. 0 | page 20 of 20 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06223-0-1/07(0)

▲Up To Search▲

Price & Availability of ADF4113HV

	To Download ADF4113HV Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .